This invention relates generally to sense amplifiers. More particularly, the present invention relates to a sense amplifier for use in an integrated circuit memory that is compensated for current and resistive load imbalances.
A prior art cross-coupled sense amplifier is shown in FIG. 1. Sense amplifier 10 includes first and second P-channel transistors 20 and 22. The sources of transistors 20 and 22 are coupled to a VDD power node, which is energized typically by a five volt, 3.3 volt, or three volt power supply. The gates and drains of P-channel transistors 20 and 22 are cross-coupled to form the sensing nodes for one half of the sense amplifier and are coupled to bit node 16 and complementary bit node 18. The cross-coupling of transistors 20 and 22 provides positive feedback for amplifying small charges developed on bit lines 16 and 18 into full complementary logic levels. Similarly, sense amplifier 10 also includes first and second N-channel transistors 24 and 26. The sources of transistors 24 and 26 are coupled to a ground node, which is typically zero volts, but could also be a voltage less than the VDD voltage, including negative voltages. The gates and drains of N-channel transistors 24 and 26 are also cross-coupled to form the sensing nodes for the other half of the sense amplifier and are also coupled to bit node 16 and complementary bit node 18. The cross-coupling of transistors 24 and 26 also provides positive feedback for amplifying small charges developed on bit lines 16 and 18 into full complementary logic levels.
Referring now to FIG. 2, a plan view of a prior art layout for sense amplifier 10 and a portion of a memory column is shown. Sense amplifier 10 is shown as a rectangle including portions 24, 26, 20 and 22 corresponding to the transistors shown in FIG. 1. A column of representative memory cells 28 are shown. In operation, one of the memory cells 28 in the column shown in FIG. 2 is selected and its complementary data state is resolved into full logic levels by sense amplifier 10. Note that in FIG. 2, the layout of sense amplifier 10 is "in pitch", meaning that the width of the entire sense amplifier is contained within the width of one column of memory cells 28. While this is advantageous as far as the integrated circuit layout is concerned, there are serious corresponding disadvantages concerning electrical performance. Specifically, the imbalance in the parasitic interconnect resistances due to the strict layout confines results in a built-in voltage offset that can affect the sensitivity of the sense amplifier.
What is desired, therefore, is a circuit and method for compensating a cross-coupled sense amplifier to optimize electrical performance and increase sensitivity.